The development of the art of micro photolithography in connection with the manufacture of integrated circuits, for example LSI circuits has lead to a revolution in commercial and consumer electronics and related devices. In general, such circuits are formed by repeated exposure of a surface of a semiconductor chip to steps of producing patterns on the chip surface by coating the surface with a suitable photosensitive resist, using masks to expose the resist to the complex patterns and to create etching resist patterns, then chemically etching the surface pattern to form a "layer" of circuit elements and connections. Such well known procedures operate substantially on one or both (front and back) of the major chip surfaces. In combination with these steps, there may be selective coating of patterns onto the chip surface(s).
An extension of those general techniques is described in U.S. Pat. No. 4,930,347 issued 5 Jun. 1990 and assigned to the University of Cincinnati to produce a microanemometer. This and other various attempts have been suggested in the prior art to construct micro-miniature electronic elements, such as precision resistors, for use as sensors adaptable to signalling the flow of fluids through conduits, vents, etc., but these devices have traditionally utilized techniques which build upon or cut into the surface of a crystal wafer. Problems are encountered with sufficient thermal isolation. These techniques also encounter problems of attachment of exterior elements to a surface of the wafer, and in general to increasing the bulk of the resulting element, whereas the desired result is to minimize such bulk, and to present as small as possible an exterior with a smooth as possible a surface configuration.
A technique for selective internal etching (chamber etching) is generally described in a master's thesis by G. Burton, December 1981, which is on file in the Engineering Library of the University of Cincinnati, located in Cincinnati, Ohio. This paper describes the steps to be used for such chamber etching in a single crystal silicon wafer, but does not recognize nor address the thermal transfer considerations that may be important in the building of such elements. The Burton thesis describes only briefly the chamber etching process, showing some small bridges created with it. The doping concentration was given in terms of time with a PClO.sub.3 source. Since the time of Mr. Burton's work, use of the PClO.sub.3 gaseous phosphorous source has been recognized as dangerous, and instead many fabricators use a solid source phosphorous wafer, such as made by The Carborundum Company, as the diffusion source.
The amount of phosphorous diffused into a silicon wafer from a solid source is a function of several things, namely the temperature of the diffusion, the length of time of the diffusion, and the type of source wafer. Since the Burton thesis recorded doping concentrations in terms of time in diffusion for the PClO.sub.3 source, it was necessary to compare that doping information to what might be currently obtainable with a solid source. Therefore, a series of chamber etching trials were performed to investigate what procedures were needed to use the chamber etching technique in a production environment.